512k x 8 static ram cy7c1049bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06501 rev. ** revised february 2, 2006 1cy7c1049bn features ? high speed ?t aa = 12 ns ? low active power ? 1320 mw (max.) ? low cmos standby powe r (commercial l version) ? 2.75 mw (max.) ? 2.0v data retention (400 w at 2.0v retention) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features functional description [1] the cy7c1049bn is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049bn is available in a standard 400-mil-wide 36-pin soj package with center power and ground (revolu- tionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 top view soj 12 13 33 36 35 34 16 15 21 22 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 5 i/o 4 a 9 a 0 i/o 0 i/o 1 i/o 2 oe a 17 a 16 a 13 ce a 9 a 18 18 17 19 20 gnd i/o 7 i/o3 i/o 6 v cc a 10 a 11 nc nc a 10 [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 2 of 10 note: 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress application note, available on t he internet at www.cypress.com. maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c1049bn-12 7c1049bn-15 7c1049bn-17 7c1049bn-20 7c1049bn-25 maximum access time (ns) 12 15 17 20 25 maximum operating current (ma) 240 220 195 185 180 maximum cmos standby current (ma) com?l 8 8 8 8 8 com?l/ind?l l- - 0.5 0.5 0.5 ind?l - - - 9 9 operating range range ambient temperature v cc commercial 0 c to +70 c 4.5v?5.5v industrial ?40 c to +85 c electrical characteristics over the operating range parameter description test conditions 7c1049b-12 7c1049b-15 7c1049b-17 min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3 2.2 v cc +0.3 2.2 v cc +0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 ?0.3 0.3 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max. , f = f max = 1/t rc 240 220 195 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 40 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l 8 8 8 ma com?l l - - 0.5 ma ind?l - - 8 ma ind?l l - - 0.5 ma note: 2. minimum voltage is?2.0v for pulse durations of less than 20 ns. [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 3 of 10 electrical characteristics over the operating range (continued) test conditions 7c1049b-20 7c1049b-25 parameter description min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max. , f = f max = 1/t rc 185 180 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l 8 8 ma com?l l 0.5 0.5 ma ind?l 8 8 ma ind?l l 0.5 0.5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8pf c out i/o capacitance 8 pf ac test loads and waveforms note: 3. tested initially and after any design or proc ess changes that may affect these parameters. 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 3 ns 3 ns output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 4 of 10 switching characteristics [4] over the operating range 7c1049b-12 7c1049b-15 7c1049b-17 parameter description min. max. min. max. min. max. unit read cycle t power v cc (typical) to the first access [5] 111ms t rc read cycle time 12 15 17 ns t aa address to data valid 12 15 17 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 12 15 17 ns t doe oe low to data valid 6 7 8 ns t lzoe oe low to low z [7] 000ns t hzoe oe high to high z [6, 7] 677ns t lzce ce low to low z [7] 333ns t hzce ce high to high z [6, 7] 677ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 12 15 17 ns write cycle [8, 9] t wc write cycle time 12 15 17 ns t sce ce low to write end 10 12 12 ns t aw address set-up to write end 10 12 12 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 10 12 12 ns t sd data set-up to write end 7 8 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [7] 333ns t hzwe we low to high z [6, 7] 678ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. this part has a voltage regulator which steps down the voltage from 5v to 3.3v internally. t power time has to be provided initially before a read/write operation is started. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 5 of 10 switching characteristics [4] over the operating range (continued) parameter description 7c1049b-20 7c1049b-25 unit min. max. min. max. read cycle t power v cc (typical) to the first access [5] 111 t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha data hold from address change 3 5 ns t ace ce low to data valid 20 25 ns t doe oe low to data valid 8 10 ns t lzoe oe low to low z [7] 00ns t hzoe oe high to high z [6, 7] 810ns t lzce ce low to low z [7] 35ns t hzce ce high to high z [6, 7] 810ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 20 25 ns write cycle [8] t wc write cycle time 20 25 ns t sce ce low to write end 13 15 ns t aw address set-up to write end 13 15 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 13 15 ns t sd data set-up to write end 9 10 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [7] 35ns t hzwe we low to high z [6, 7] 810ns data retention characteristics over the operating range parameter description conditions [11] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current com?l l v cc = v dr = 3.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 200 a ind?l 1 ma t cdr [3] chip deselect to data retention time 0 ns t r [10] operation recovery time t rc ns notes: 10. t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 and slower speeds. 11. no input may exceed v cc + 0.5v. [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 6 of 10 data retention waveform switching waveforms read cycle no. 1 [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 7 of 10 write cycle no. 1 (ce controlled) [15, 16] write cycle no. 2 (we controlled, oe high during write) [15, 16] notes: 15. data i/o is high impedance if oe = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 17. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 17 [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 8 of 10 write cycle no. 3 (we controlled, oe low) [16] truth table ce we oe inputs/outputs mode power h x x high z power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z selected, output disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 cy7c1049bn-12vc 51-85090 36-lead (400-mil) molded soj commercial cy7c1049bn-12vxc 51-85090 36-lead (400-mil) molded soj (pb-free) 15 cy7c1049bn-15vc 51-85090 36-lead (400-mil) molded soj cy7c1049bn-15vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bn-15vi 51-85090 36-lead (400-mil) molded soj industrial cy7c1049bn-15vxi 51-85090 36-lead (400-mil) molded soj (pb-free) 17 cy7c1049bn-17vc 51-85090 36-lead (400-mil) molded soj commercial cy7c1049bnl-17vc 51-85090 36-lead (400-mil) molded soj CY7C1049BN-17VXC 51-85090 36-lead (400-mil) molded soj (pb-free) 20 cy7c1049bn-20vc 51-85090 36-lead (400-mil) molded soj cy7c1049bnl-20vc 51-85090 36-lead (400-mil) molded soj cy7c1049bn-20vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bn-20vi 51-85090 36-lead (400-mil) molded soj industrial cy7c1049bn-20vxi 51-85090 36-lead (400-mil) molded soj (pb-free) 25 cy7c1049bnl-25vc 51-85090 36-lead (400-mil) molded soj commercial cy7c1049bn-25vi 51-85090 36-lead (400-mil) molded soj industrial cy7c1049bn-25vxi 51-85090 36-lead (400-mil) molded soj (pb-free) please contact local sales representative regarding availability of these parts. switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 17 [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagram 36-lead (400-mil) molded soj (51-85090) 51-85090-*b [+] feedback [+] feedback
cy7c1049bn document #: 001-06501 rev. ** page 10 of 10 document history page document title: cy7c1049bn 512k x 8 static ram document number: 001-06501 rev. ecn no. issue date orig. of change description of change ** 424111 see ecn nxr new data sheet [+] feedback [+] feedback
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